Evolution of the Silicon Wafer

EVOLUTION OF THE SILICON WAFER (F450C F450C 775 725 675 2012 2013 July 2014 First 450 mm wafers patterned with immersion lithography displayed at SEMICON West. 969 1972 1976 1981 1983 1992 2002 2011 2014 March 2015 450 mm notchless wafer standardization announced. SUNY Poly CNSE Announces F450C member M+W Group's expansion of U.S. headquarters at Albany NanoTech Complex. F450C member Ovivo completes the delivery of a state-of-the-art ultra-pure water plant expansion for the new 450 mm cleanroom facilities at SUNY Poly CNSE. 100 mm July 2015 World's first-ever 450 mm immersion scanner, the Nikon NSR-S650D, installed at SUNY Poly CNSE. At SEMICON West, G450C displays one of the first patterned notchless 450 mm wafers with Cu metallization and 1.5 mm edge exclusion. 450 mm 1960 – 23 mm 1960 – 25 mm 1963 – 28 mm M+W GROUP F450C: Defining next-generation facility solutions for OVIVO 450 mm wafer advancement The Facilities 450 Consortium (F450C) brings together select companies for the purpose of enabling optimized 450 mm high-volume semiconductor facility design, construction and operation. The F450C cooperative model leverages industry alignment and collaboration as a critical enabler. AIR LIQUIDE What is the 450 mm Transition? The transition from 300mm-diameter to 450 mm-diameter silicon wafers in semiconductor fabrication will produce over twice the number of chips per ch2m: wafer as a means for cost reduction in high-volume manufacturing. We are now at the point where the transition to 450 mm has become imperative to the continuing success of the semiconductor industry. This has led to the foundation of an industry/government partnership called the Global 450 Consortium (G450C) that is tasked with creating a path for new equipment and materials for this new wafer size. In parallel, the F450C emerged to develop the equivalent technologies for facilities. O Haus What is driving the industry to larger wafer sizes? BUSCH Economic factors driving transitions to larger wafer sizes in semiconductor manufacturing The economies of scale result in reduced fab cost per chip when more chips are made on larger-diameter wafers, while the economies of industrial supply chains create financial risks when more chips are made in parallel on larger wafers. Consequently, when sustained global demand for certain chip types reaches thresholds, companies building and running fabs to produce such chips can reduce overall costs by transitioning to the next wafer size. Swagelok What is the F450C? EDWARDS • First-of-its-kind partnership of leading nanoelectronic facility companies, based at the NanoTech Complex of SUNY Polytechnic's College of Nanoscale Science and Engineering (CNSE). • Multiple-company consortium guiding the effort to design and build next-generation wafer-size fabrication facilities • Partner of the G450C CS CLEAN SYSTEMS PFEIFFER VACUUM anhounced the establishment of G450C SUNT Poly CNSE's Albany 625 525 375 Silicon wafer thickness evolution (um) → 275 May 2012 ident Barack Obama visits SUNY y CNSE's Albany NanoTech Complex. Pol New York Governor Andrew M. Cuomo Silicon wafer size evolution (mm) NanoTech Complex. sapunouup oIona J O ELOZ aunr of F450C. 096 July 2013 Nikon receives order for 450 mm immersion scanner from G450C. 2015 1969 – 50 mm 2016 1972 - 75 mm 125 mm – 1981 1976 – 100 mm 150 mm - 1983 200 mm – 1992 300 mm - 2002 450 mm